IC Layout:

Responsible for the whole IC mask design process: from chip layer planning, layered layout, top-level wiring, layout verification and fracture data generation to bond graph creation;

1. Be able to work independently to design the wiring of analog, digital and power management IC, from the initial layout to the final streaming;

2. Master cadence virtuoso XL, have strong analysis ability, and be able to interpret Assura / PVS verification report independently, so as to accelerate IC physical design;

3. Be able to design the layout of simulator components to achieve the best matching. Can design the arrangement of power metal bus to meet the requirements of current and noise. Have a global idea to create chip size within the target range of product cost;

4. Be familiar with the design rules of process layer and wafer factory;

5. Good communication skills and cooperation with IC designers;

6. Be able to adapt to fast-paced working environment;

CAD/CAM:

1. DRC / LVS / LPE command file development and maintenance;

2. Virtuoso script development and maintenance;

3. CAD application maintenance;

4. Installation and maintenance of foundry PDK;

5. Professional knowledge and working experience of IC film;

1. More than 5 years of analog, mixed signal and power management IC wiring experience in CMOS, BiCMOS and BCD. Familiar with 0.25um, 0.18um, 0.13um process;

2. Master degree or above;